Analog-to-digital conversion apparatus and method

ABSTRACT

A properly level-controlled digital signal can be obtained every sample. An input signal is supplied to amplifiers having their gains of one, two, four and eight. Outputs of the amplifiers are converted to digital signals at the same time in corresponding A/D converters having the same characteristic, respectively, and inputted to a data selection part. In the data selection part, when an input signal is high level, one A/D converter to which is inputted the input signal passing through the corresponding amplifier having its large gain, overflows so that the overflow-bit thereof becomes “1”. The output digital signal of the A/D converter is selected and outputted, which is connected to the amplifier having the largest gain among the amplifiers connected to corresponding A/D converters each of which has its overflow-bit is “0”. The digital signal is corrected in its scale and outputted.

TECHNICAL FIELD

The present invention relates to an analog-to-digital conversionapparatus and an analog-to-digital conversion method for converting aninput signal to a digital signal, and more particularly, toanalog-to-digital conversion apparatus and method that are capable ofconverting an input signal the dynamic range in signal level of which iswide and the frequency of which is comparatively high to a digitalsignal.

BACKGROUND ART

In a spectrum analyzer, network analyzer, or the like, for example,there is carried out such a procedure that an input signal is convertedto an intermediate frequency signal the frequency of which is one in therange of, for example, 1 MHz to 21.4 MHz or so and then the intermediatefrequency signal is converted to a digital signal. In such case, thereis required an analog-to-digital conversion apparatus (hereinafter,referred to as A/D conversion apparatus) for converting an input signalto a digital signal, the A/D conversion apparatus having its dynamicrange greater than 100 dB as well as higher or faster sampling rate than42.8 MSa/s (million samples per second). An A/D conversion apparatusthat fulfils such requirements is much costly.

An A/D conversion apparatus in which the above-mentioned problem can besolved has been proposed in U.S. Pat. No. 5,844,512 (issued on Dec. 1,1998). FIG. 1 is a block diagram showing a simplified construction of anA/D conversion apparatus shown in FIG. 4 of U.S. Pat. No. 5,844,512, andthere will be now described an outline of the construction and theoperation of this A/D conversion apparatus with reference to FIG. 1.

As shown in FIG. 1, an input signal from an input terminal 11 issupplied to an anti-aliasing filter 12 and an envelope detector 14. Aninput signal that has passed through the anti-aliasing filter 12 issupplied to a variable gain amplifier 13. On the other hand, an inputsignal inputted to the envelope detector 14 is detected in its envelopeby the detector 14, and the detected output is inputted to a gaincontroller 15 as a proposed gain. The gain controller 15 refers to anoutput level of the envelope detector 14 and a gain set in the variablegain amplifier 13 to alter and set the gain of the variable gainamplifier 13 so that the output level of the variable gain amplifier 13comes within a predetermined range. Further, the envelope detector 14corresponds to the proposed gain detector 48 shown in FIG. 4 of U.S.Pat. No. 5,844,512, and also the gain controller 15 corresponds to thegain setting rule processor 50 shown in FIG. 4 of U.S. Pat. No.5,844,512.

In such manner as stated above, an input signal is amplified in thevariable gain amplifier 13 to a signal the level of which comes withinthe predetermined range, and the amplified signal is supplied to asample-and-hold circuit 16. In the sample-and-hold circuit 16, an outputsignal from the variable gain amplifier 13 is sampled by a samplingclock CK_(S) and the sampled value or data is held therein. The sampledvalue held in the sample-and-hold circuit 16 is converted by ananalog-to-digital converter (hereinafter, referred to as A/D converter)17 to a digital signal (digital value) which is, in turn, supplied to acorrection processing part 18. The correction processing part 18corrects an inputted digital signal by referring to a look-up table 19in accordance with an output signal from the gain controller 15. Forexample, the correction processing part 18 will correct an error in adigital signal that is caused by a shift in the input-outputcharacteristic of the variable gain amplifier 13 from an idealcharacteristic thereof, and further, will correct an inputted digitalsignal to a digital signal showing a level of the input signal before itis amplified by the variable gain amplifier 13 depending upon a gain setto the variable gain amplifier 13. The corrected digital signal isoutputted to an output terminal 21 of the correction processing part 18.Further, the correction processing part 18 corresponds to the scalingprocessor 64 shown in FIG. 4 of the above-stated U.S. Pat. No.5,844,512.

In the prior art A/D conversion apparatus shown in FIG. 1, the level ofan input signal is detected by the envelope detector 14 and the gain ofthe variable gain amplifier 13 is set depending upon the detected level.Since the envelope detector 14 has a time constant so that a time delayor lag occurs, in the prior art, the anti-aliasing filter 12 is insertedbefore the variable gain amplifier 13 to remove any aliasing as well asan input signal is delayed by delay means to match a timing when thesignal is inputted to the variable gain amplifier 13 to a timing whenthe detected level of the input signal is inputted to the gaincontroller 15 so that the level of the input signal can be controlled bythe variable gain amplifier 13. However, an input signal undergoes adistortion by the anti-aliasing filter 12 or a delay line unless thegroup delay thereof is constant and also the frequency characteristic inthe amplitude is constant so that it is difficult to convert an inputsignal to a digital signal with high accuracy.

In addition, since an input signal is detected in its envelope so thatthe level thereof is detected, as shown in FIG. 2A, for example, when aninput signal shown by a solid line 22 is supplied, the gain is set toeight times at the level L1, four times at the level L2, twice at thelevel L3, and one at the level L4 as shown a broken line 23, and thegain is changed every plural samples. An example of a sample point 24 isillustrated in FIG. 2A by a black point or dot. For this reason, in caseof inputting a signal obtained by sweeping or varying the frequency ofan input signal; converting the signal to a digital signal; multiplyingthe digital signal by a digital sine wave signal and a digital cosinewave signal; obtaining the sum of squares of these multiplied values;and finding the frequency characteristic in the amplitude of the inputsignal, there is obtained, for instance, a waveform the level of whichvaries stepwise at points 25 where the gain of the variable gainamplifier 13 is changed, that is, a discontinuous waveform as shown inFIG. 2B, and hence a correct display of waveform cannot be obtained.

Moreover, when the gain of the variable gain amplifier 13 is changed, awhisker-like noise (impulse-like noise) or noises are generated in theamplified output signal. If this noise portion should be sampled in thesample-and-hold circuit 16, the noise is sampled so that a false digitalsignal is outputted.

DISCLOSURE OF THE INVENTION

An object of the present invention is to provide an A/D conversionapparatus that is able to solve the above-stated prior art problems.

Another object of the present invention is to provide ananalog-to-digital conversion method by which the above-stated prior artproblems can be solved.

In order to attain the foregoing objects, in an aspect of the presentinvention, there is provided an analog-to-digital conversion apparatuscomprising: at least one level controller that controls the level of aninput signal; at least one analog-to-digital converter; and selectionmeans that outputs, depending upon the magnitude of the level of aninput signal, a digital signal obtained by digital-converting the inputsignal or obtained by digital-converting the input signal after thelevel of the input signal is controlled.

In accordance with one mode of the present invention, there areprovided, as the analog-to-digital converter, an analog-to-digitalconverter for converting an input signal the level of which is notcontrolled to a digital signal and at least one analog-to-digitalconverter for converting a signal the level of which is controlled bycorresponding level controller to a digital signal, and the selectionmeans selects and outputs one of the digital signals convertedrespectively by the plural analog-to-digital converters depending uponthe digital signals.

The aforesaid selection means may be means that selects, in case theplural analog-to-digital converters are ranked in order of themagnitudes of the levels of input signals inputted thereto, the outputdigital signal of the analog-to-digital converter the overflow-bit ofwhich is “0” and the rank of which is immediately lower than that of theanalog-to-digital converter the overflow-bit of the output digitalsignal of which is “1”, or alternatively, the selection means maycomprise: a plurality of comparators each comparing the digital signalof each analog-to-digital converter with a reference value; and meansthat selects, in case the plural analog-to-digital converters are rankedin order of the magnitudes of the levels of input signals inputtedthereto, the output digital signal of the analog-to-digital convertercorresponding to one of the comparators the output of which is lowerthan the reference value as well as the rank of which is immediatelylower than that of the analog-to-digital converter corresponding toanother one of the comparators the output of which is higher than thereference value.

In accordance with another mode of the present invention, there areprovided as the analog-to-digital converter a first analog-to-digitalconverter for converting the input signal the level of which is notcontrolled to a digital signal and a second analog-to-digital converterfor converting a signal the level of which is controlled by thecorresponding level controller to a digital signal, and the selectionmeans is means that selects and outputs at once the digital signaloutputted from the first analog-to-digital converter when theoverflow-bit of the digital signal outputted from the secondanalog-to-digital converter for converting a signal the level of whichis controlled to a digital signal, changes from “0” to “1” and thatremains the selection of the digital signal outputted from the firstanalog-to-digital converter in case even the overflow-bit of the digitalsignal outputted from the second analog-to-digital converter changesfrom “1” to “0” if the state of “0” changes to “1” within a preset time.

In accordance with still another mode of the present invention, there isprovided as the analog-to-digital converter one main analog-to-digitalconverter, and the selection means comprises: a range selectionanalog-to-digital converter the resolution of which is lower than thatof the main analog-to-digital converter and to which the input signal isinputted; and a selection switch part for supplying to the mainanalog-to-digital converter an output signal from one level controlleror the input signal the level of which is not controlled, depending upona digital signal converted by the range selection analog-to-digitalconverter.

As the level controller, there may be used a level controller the gainof which is fixed or a level controller the gain of which is previouslysettable.

In another aspect of the present invention, there is provided ananalog-to-digital conversion method comprising the steps of: convertingto a digital signal an input signal the level of which is lower after itis controlled in its level, or an input signal the level of which ishigher without controlling its level or after it is controlled in itslevel; and selecting a digital signal based on the input signal thelevel of which is higher when the overflow-bit of a digital signal basedon the input signal the level of which is lower is “1”, and selecting adigital signal based on the input signal the level of which is lowerwhen the overflow-bit of a digital signal based on the input signal thelevel of which is lower is “0”.

In accordance with one preferred mode of the present invention, theselecting step further includes the step of selecting, when theoverflow-bit of a digital signal based on the input signal the level ofwhich is lower changes from “0” to “1”, a digital signal based on theinput signal the level of which is higher at once, and remaining theselection of a digital signal based on the input signal the level ofwhich is higher, in case even the overflow-bit of a digital signal basedon the input signal the level of which is lower changes from “1” to “0”if the state of “0” changes to “1” within a preset time.

According to the present invention, for each sample of an input signal,a level range suitable for the input signal is determined, and the inputsignal is converted to a digital signal after it is controlled in itslevel in accordance therewith or without controlling its level.Therefore, there is no need to use any envelope detector and any gaincontroller like the prior art, and so any input signal can be convertedto a digital signal with high precision. In addition, every pluralsamples, the gain of the amplifier is not controlled like the prior art,but an input signal is amplified by each amplifier and converted to adigital signal, and this converted digital signal is selected. As aresult, a higher accurate digital signal is obtained, and yet, there isno possibility that any whisker-like or impulse-like noise is generateddue to control of the gain.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a prior art A/D conversion apparatus.

FIG. 2A is a waveform diagram for explaining a waveform of an inputsignal and a manner of gain control in the A/D conversion apparatusshown in FIG. 1.

FIG. 2B is a diagram showing one example of the amplitude-frequencycharacteristic of an input signal in the A/D conversion apparatus shownin FIG. 1.

FIG. 3 is a block diagram showing a first embodiment of the A/Dconversion apparatus according to the present invention.

FIG. 4 is a block diagram showing one example of the data selection partin the A/D conversion apparatus shown in FIG. 3.

FIG. 5 is a block diagram showing another example of the data selectionpart in the A/D conversion apparatus shown in FIG. 3.

FIG. 6 is an illustration showing one example of the selectedinformation in the data selection part.

FIG. 7A is an illustration showing a waveform and sample points forexplaining the effects of the present invention.

FIG. 7B is an illustration for explaining a manner of gain control inthe A/D conversion apparatus according to the present invention.

FIG. 8 is a block diagram showing a second embodiment of the A/Dconversion apparatus according to the present invention.

FIG. 9 is an illustration showing a relationship between an output fromthe range selection A/D converter and the gain of an amplifier to beselected in the A/D conversion apparatus shown in FIG. 8.

FIG. 10 is an illustration showing a relationship between a samplingclock CK_(S) for the main A/D converter and a range selection clockCK_(A) in the A/D conversion apparatus shown in FIG. 8.

FIG. 11 is a block diagram showing a third embodiment of the A/Dconversion apparatus according to the present invention.

FIG. 12 is an illustration for explaining the operation of the A/Dconversion apparatus shown in FIG. 11.

FIG. 13 is a timing chart for explaining the operation of the A/Dconversion apparatus shown in FIG. 11.

FIG. 14 is a block diagram showing a fourth embodiment of the A/Dconversion apparatus according to the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

The preferred embodiments of the present invention will now be describedin detail with reference to the accompanying drawings. The presentinvention may, however, be embodied in many different forms and shouldnot be construed as limited to the embodiments set forth hereinafter;rather, the embodiments are provided so that this disclosure will bethorough and complete, and will fully convey the scope of the inventionto those skilled in the art.

At first, a first embodiment of the A/D conversion apparatus accordingto the present invention will be described in detail with reference toFIGS. 3 to 7.

FIG. 3 is a block diagram showing the first embodiment of the A/Dconversion apparatus according to the present invention. An input signalfrom an input terminal 31 is supplied, after it has passed through ananti-aliasing filter 32, to four amplifiers (or four level controllersthat differ in their control variables from one another) 33-1 to 33-4that differ in their gains from one another, in this first embodiment.The gains of the four amplifiers 33-1 to 33-4 are fixed, and the gain ofthe first amplifier 33-1 is set to one (1), the gain of the secondamplifier 33-2 is set to two (2), the gain of the third amplifier 33-3is set to four (4), and the gain of the fourth amplifier 33-4 is set toeight (8). These gains are merely by way of example, and they may be setto other values or may be set to another values except for values of thepower of 2 as in the above example.

Outputs from the four amplifiers 33-1 to 33-4 are supplied tocorresponding A/D converters 34-1 to 34-4, respectively. These A/Dconverters 34-1 to 34-4 have the same characteristic, that is, they areconfigured such that the convertible range in level of each of the A/Dconverters 34-1 to 34-4 is the same as well as they have the sameresolution, and they are operated by the same clock CK_(S) supplied froma clock terminal 35 thereby to convert outputs from the correspondingamplifiers 33-1 to 33-4 to digital signals with required resolutionswithin their convertible level ranges. In addition, though not shown inthe figure, each of the A/D converters 34-1 to 34-4 is provided with thesample-and-hold circuit 16 of the prior art A/D conversion apparatusshown in FIG. 1 built therein. Further, in case the sample-and-holdcircuit is not built therein, it is inserted before each of the A/Dconverters 34-1 to 34-4.

Output digital signals from the A/D converters 34-1 to 34-4 are inputtedto a data selection part 36. The data selection part 36 selects a properdigital signal corresponding to the magnitude in level of the inputsignal from the input terminal 31 and supplies the selected digitalsignal to a correction processing part 37. In this embodiment, the dataselection part 36 utilizes digital signals from the A/D converters 34-1to 34-4 to select an output digital signal from one of the A/Dconverters 34-1 to 34-4, the one A/D converter corresponding to themagnitude in level of the input signal. In other words, a pre-estimatedfluctuation range in the levels of input signals are divided into pluralranges, four ranges in this example, and the data selection part 36selects, depending upon to which divided level range the level of aninput signal belongs, an output digital signal from the correspondingA/D converter.

As is well known, each of the A/D converters 34-1 to 34-4 overflows whenthe level of an input signal thereto is beyond the convertible levelrange thereof so that the overflow-bit of the converted output digitalsignal becomes “1”. That is, each of the A/D converters 34-1 to 34-4 tothe input of which is connected the corresponding amplifier thatamplifies an input signal from the input terminal 31 too much so thatthe amplified signal becomes beyond the operation range of thecorresponding A/D converter, outputs a digital signal having itsoverflow-bit of “1”. Accordingly, the A/D converters 34-1 to 34-4 areranked in such manner that the first or highest rank is given to an A/Dconverter to which an output of the amplifier having the greatest gainis inputted, the second rank is given to an A/D converter to which anoutput of the amplifier having the second greater gain is inputted, thethird rank is given to an A/D converter to which an output of theamplifier having the third greater gain is inputted, . . . , the lowestrank is given to an A/D converter to which an output of the amplifierhaving the lowest gain is inputted. In this example, the first rank isgiven to the fourth A/D converter 34-4, the second rank is given to thethird A/D converter 34-3, and so on. With such arrangement as statedabove, if the data selection part 36 searches or checks the A/Dconverters 34-1 to 34-4 in order of the ranks from the highest rank asto whether there is an A/D converter the output digital signal of whichhas the overflow-bit of “1”, and it selects the first A/D converter theoutput digital signal of which has no overflow-bit, that is, the firstA/D converter the output digital signal of which has the overflow-bit of“0”, the output digital signal of the proper or correct A/D convertercan be selected.

This searching of presence of the overflow-bit may be equivalent to areverse searching that the data selection part 36 searches or checks theA/D converters 34-1 to 34-4 in order of the ranks from the lowest rank,that is, from the lowest rank A/D converter having its overflow-bit of“0”, as to whether there is an A/D converter the output digital signalof which has the overflow-bit of “1”, and it selects an A/D converterimmediately lower in rank than the first A/D converter the outputdigital signal of which has the overflow-bit of “1”. In other words, thedata selection part selects an output data of an A/D converter to whichis connected an amplifier having its gain lower by one rank than anamplifier the gain of which is the lowest among amplifiers each beingconnected to corresponding A/D converter having its overflow-bit of “1”.Speaking the other way round, the data selection part may select anoutput data of an A/D converter to which is connected an amplifierhaving its gain that is the greatest among amplifiers each beingconnected to corresponding A/D converter having its overflow-bit of “0”.

Selection of a proper A/D converter by utilization of an overflow-bit asdiscussed above can be carried out by use of the data selection part 36that is constructed in circuit, for example, as shown in FIG. 4. Asshown in FIG. 4, output digital signals of the first to the fourth A/Dconverters 34-1 to 34-4 are supplied to a first to a fourthcorresponding gates 38-1 to 38-4, respectively. The overflow-bit of thefourth A/D converter 34-4 is supplied to the control terminal of thefourth gate through an inverter 39-4 as well as supplied to thenon-inverting input terminal of a third AND circuit 39-3 to theinverting input terminal of which is supplied the overflow-bit of thethird A/D converter 34-3. In addition, the overflow-bit of the third A/Dconverter 34-3 is also supplied to the non-inverting input terminal of asecond AND circuit 39-2 to the inverting input terminal of which issupplied the overflow-bit of the second A/D converter 34-2. Theoverflow-bit of the second A/D converter 34-2 is also supplied to thenon-inverting input terminal of a first AND circuit 39-1 to theinverting input terminal of which is supplied the overflow-bit of thefirst A/D converter 34-1. Also, outputs of the first, second and thirdAND circuits 39-1, 39-2 and 39-3 are supplied to control terminals ofthe first, second and third gates 38-1, 38-2 and 38-3, respectively.

With the construction as mentioned above, depending upon into whichdivided range the level of an input signal enters, only an outputdigital signal of one A/D converter to which is connected an amplifierthe gain of which is proper, can pass through one of the four gates 38-1to 38-4. For example, in case the level of an input signal amplified bythe second amplifier 33-2 comes in the proper level range for the secondA/D converter 34-2, each of the overflow-bits of the third and fourthA/D converters 34-3 and 34-4 becomes “1” so that the output of theinverter 39-4 and the output of the third AND circuit 39-3 become “0”,and so the fourth and third gates 38-4 and 38-3 are not opened. Inaddition, each of the overflow-bits of the first and second A/Dconverters 34-1 and 34-2 becomes “0” so that the output of the first ANDcircuit 39-1 becomes “0”, and so the first gate 38-1 is also not opened.However, to the second AND circuit 39-2 are inputted the overflow-bit of“1” from the third A/D converter 34-3 and the overflow-bit of “0” fromthe second A/D converter 34-2 which is, in turn, inverted to “1”.Accordingly, the output of the second AND circuit 39-2 becomes “1” andhence only the second gate 38-2 is opened. As a result, only the outputdigital signal of the second A/D converter 34-2 can be outputted.

There may be a case that each of the A/D converters has its linearity ofconversion that is inferior at portions near the upper and/or lowerlimit of the convertible level range thereof. Taking such fact intoconsideration, the output digital signal of the proper A/D converter maybe selected by use of the data selection part 36 that is constructed incircuit, for example, as shown in FIG. 5.

In the circuit construction shown in FIG. 5, there are provided aregister 41 in which reference values are set as well as first to fourthdigital comparators 42-1 to 42-4, and each of the reference values setin the register 41 and the output digital signal of corresponding one ofthe first to fourth A/D converters 34-1 to 34-4 are compared incorresponding one of the digital comparators 42-1 to 42-4. The outputsof the first to third comparators 42-1 to 42-3 are supplied to theinverting input terminals of first to third AND circuits 43-1 to 43-3,respectively, and the outputs of the second to fourth comparators 42-2to 42-4 are supplied to the non-inverting input terminals of the firstto third AND circuits 43-1 to 43-3, respectively. In addition, theoutput of the fourth comparator 42-4 is supplied to the control terminalof the fourth gate 38-4 through an inverter 43-4, and the outputs offirst to third AND circuits 43-1 to 43-3 are supplied to the controlterminals of the first to third gates 38-1 to 38-3, respectively.

Here, each of the reference values set in the register 41 is selected tobe a value that is equal to, for example, about 80% of the upper limitvalue of the convertible level range of each of the A/D converters 34-1to 34-4. In addition, it is assumed that the first to fourth comparators42-1 to 42-4 output “1” if the digital signals from the correspondingfirst to fourth A/D converters 34-1 to 34-4 are greater than thecorresponding reference values, respectively, and that output “0” if thedigital signals from the corresponding first to fourth A/D converters34-1 to 34-4 are shorter than the corresponding reference values,respectively.

With the construction as stated above, like the data selection part asdescribed above with reference to FIG. 4, in case the output of thesecond amplifier 33-2 exists within the proper convertible level rangefor the second A/D converter 34-2, for example, each of the outputs ofthe first and second comparators 42-1 and 42-2 becomes “0” and each ofthe outputs of the third and fourth comparators 42-3 and 42-4 becomes“1” so that the input conditions of the first to third AND circuits 43-1to 43-3 and the input condition of the inverter 43-4 are identical withthose of the first to third AND circuits 39-1 to 39-3 and the inverter39-4 in the data selection part shown in FIG. 4, and hence only thesecond gate 38-2 is opened. As a result, only the output digital signalof the second A/D converter 34-2 can be selected. Further, in case ofselecting a digital signal by utilization of the outputs of the first tofourth comparators 42-1 to 42-4 discussed above, there may be used in asimilar way the above-stated various selection means or techniques eachutilizing the overflow-bit.

The one digital signal that is selected as described above from theoutput digital signals of the first to fourth A/D converters 34-1 to34-4 is sent to the correction processing part 37. This correctionprocessing part 37 has a characteristic correction part 46 and a scalecorrection part 48 provided therein in this embodiment and isconstructed such that the digital signal inputted to the correctionprocessing part 37 may be scaled down or up in the scale correction part48, if necessary, so that it has the same value as that of a digitalsignal in case it is directly converted from an input signal transmittedto the input terminal 31, and/or in the characteristic correction part46, in case the input-output characteristic of each of the amplifiers33-1 to 33-4 is not always different from a predetermined gain, thecorrection therefor may be carried out, if necessary.

These corrections are executed by referring to first to fourth look-uptables 45-1 to 45-4 that are provided in correspondence to the first tofourth amplifiers 33-1 to 33-4, respectively. For example, in case theoutput digital signal of the second A/D converter 34-2 is selected bythe data selection part 36, selection information indicating the factthat the output digital signal of the second A/D converter 34-2 has beenselected is transmitted to the correction processing part 37 from thedata selection part 36, and so the second look-up table 45-2corresponding to the second amplifier 33-2 is referred by thistransmission of the selection information. The characteristic correctionpart 46 of the correction processing part 37 is configured such that itobtains correction data relating to the characteristic of the secondamplifier 33-2 with reference to the corresponding second look-up table45-2, and corrects the characteristic of the digital signal inputtedthereto so that a digital signal is read out therefrom, which is thesame as a digital signal obtained by that an input signal to the secondamplifier 33-2 is amplified by its proper accurate gain set in thesecond amplifier 33-2, a signal amplified by double in this example, andthat the amplified signal is converted to a digital signal in the secondA/D converter 34-2. The scale correction part 48 is configured such thatit obtains correction data relating to the scale with reference to thecorresponding second look-up table 45-2, and that corrects in scale thedigital signal the characteristic of which has been corrected so that itbecomes a digital signal corresponding to the input signal transmittedto the input terminal 31.

In order to generate the above-stated selection information suppliedfrom the data selection part 36 to the correction processing part 37, inthe circuit constructions shown in FIGS. 4 and 5, for instance, thecontrol signal supplied to each of the control terminals of the first tofourth gates 38-1 to 38-4 is also supplied to a selection informationgenerating part 47. This selection information generating part 47 is anencoder that converts, for example, a control signal of four bitsinputted thereto to a code of two bits, and so the selection informationgenerating part 47 encodes a control signal of four bits inputtedthereto to selection information of two bits as shown in FIG. 6, forinstance. Specifically, the selection information generating part 47outputs selection information of “00” in case the output of the firstA/D converter 34-1 to which the first amplifier 33-1 the gain of whichis one (1) is connected, is selected, outputs selection information of“01” in case the output of the second A/D converter 34-2 to which thesecond amplifier 33-2 the gain of which is two (2) is connected, isselected, outputs selection information of “10” in case the output ofthe third A/D converter 34-3 to which the third amplifier 33-3 the gainof which is four (4) is connected, is selected, and outputs selectioninformation of “11” in case the output of the fourth A/D converter 34-4to which the fourth amplifier 33-4 the gain of which is eight (8) isconnected, is selected.

Accordingly, in case of the first embodiment, the output digital signalof the second A/D converter 34-2 is selected, for example, the selectioninformation of “01” is supplied to the correction processing part 37from the data selection part 36, and therefore, the characteristiccorrection part 46 and the scale correction part 48 of the correctionprocessing part 37 can refer to the second look-up table 45-2corresponding to the second amplifier 33-2 the gain of which is two onthe basis of the selection information inputted thereto.

The scale correction processing in the scale correction part 48, thatis, the processing of correcting the scale of an input digital signal tothat of a digital signal corresponding to the input signal transmittedto the input terminal 31 can be carried out by referring to the look-uptable on the basis of the supplied selection information and dividingthe digital signal selected by the data selection part 36 by the gain ofthe amplifier connected to the A/D converter which has outputted theselected digital signal. For example, if the gain of the amplifier istwo, the digital signal is divided by two. This may be performed byshifting the digital signal rightward by one bit in the register inwhich the digital signal is stored in the scale correction part 48. Asalready described, if the gains of the first to fourth amplifiers 33-1to 33-4 are set to values such as 1, 2, 4, 8 corresponding to the powerof 2, this scale correction can be performed by merely shifting thedigital data rightward by the number of power in the register, whichresults in an advantage that the scale correction processing can be donewith ease.

Further, the selection information may be one by which the gain of theamplifier can be known in the correction processing part 37, theamplifier being connected to the A/D converter that has outputted thedigital data selected by the data selection part 36, and what kind orform of information may be used. As shown in FIG. 6, in case the fourA/D converters 34-1 to 34-4 are numbered by binary number system orbinary digits, a relationship between gains for correcting the scaledepending upon each number and binary digit numbers may be previouslydescribed in the look-up tables. Alternatively, if a relationshipbetween gains for correcting the scale depending upon each number andbinary digit numbers may be provided in the correction processing part37, the scale correction can be done in the scale correction part 48 ofthe correction processing part 37 without referring to the look-uptables.

As described above, in this first embodiment, the A/D conversionapparatus is arranged to utilize digital outputs outputted from the A/Dconverters 34-1 to 34-4 every sample to select a digital signal which isamplified by the amplifier corresponding to the most proper range for aninput signal (level range of an input signal) and converted to thatdigital signal by the corresponding A/D converter. For example, in casean input signal as shown by a solid line 22 in FIG. 7A is supplied tothe input terminal 31, assuming that the input signal 22 is sampled atpoints each being indicated by a black point or dot, portions near thesesample points 24 are shown in FIG. 7B in enlarged scale wherein the timebase is particularly enlarged. In addition, assuming that levels forchanging the level range of an input signal, that is, operation levelsfor determining that an output from which one of the amplifiers shouldbe A/D converted, are denoted by L4, L3 and L2 as shown in FIG. 7B, incase the level of an input signal is greater than L4, a digital signalis selected, which is obtained by A/D converting the output of the firstamplifier 33-1 having its gain of 1, in case the level of an inputsignal comes in the range between L3 and L4, a digital signal isselected, which is obtained by A/D converting the output of the secondamplifier 33-2 having its gain of 2, in case the level of an inputsignal comes in the range between L2 and L3, a digital signal isselected, which is obtained by A/D converting the output of the thirdamplifier 33-3 having its gain of 4, and in case the level of an inputsignal is lower than L2, a digital signal is selected, which is obtainedby A/D converting the output of the fourth amplifier 33-4 having itsgain of 8.

In such way, for each sample, an input signal is amplified by anamplifier having its gain corresponding to the level of the sample dataso that the level thereof comes within the proper convertible levelrange of the corresponding A/D converter, and then it is converted to adigital signal by the corresponding A/D converter, this digital signalbeing selected. Therefore, as compared with the case that the gain ofthe amplifier is controlled for plural samples like the prior art shownin FIG. 2A, a digital signal with higher accuracy can be obtained, andfurther, in case of making a display as shown in FIG. 2B, a waveformobtained thereby does not vary stepwise, and a continuously variedwaveform with high precision can be obtained as if it would beanalogously processed. In addition, the gain of each amplifier is notcontrolled at all, and a digital signal is selected, which is obtainedby A/D converting the output amplified by corresponding one amplifier.Accordingly, there is no possibility that any whisker-like orimpulse-like noise is generated due to control of the gain.

Further, if there are used the A/D converters 34-1 to 34-4 each having14 bits, after completion of the scale correction, quantization errorfor an input signal the level of which is equal to or greater than levelL4 becomes ½¹⁴, quantization error for an input signal the level ofwhich comes between level L3 and level L4 becomes a half of ½¹⁴,quantization error for an input signal the level of which comes betweenlevel L2 and level L3 becomes a quarter of ½¹⁴, and quantization errorfor an input signal the level of which is equal to or lower than levelL2 becomes one-eighth of ½¹⁴.

Next, a second embodiment of the A/D conversion apparatus according tothe present invention will be described in detail with reference toFIGS. 8 to 10.

FIG. 8 is a block diagram showing a second embodiment of the A/Dconversion apparatus according to the present invention, and in FIG. 8,elements and portions corresponding to those in the first embodimentwill be denoted by the same reference numbers or characters attachedthereto and explanation thereof will be omitted unless necessary. Inthis second embodiment, though an input signal from the input terminal31 is supplied, after it has passed through the anti-aliasing filter 32,to four amplifiers (or four level controllers that differ in theircontrol variables from one another) 33-1 to 33-4 that differ in theirgains from one another, there is provided only one main A/D converter 34for converting signals outputted respectively from the first to fourthamplifiers 33-1 to 33-4 to digital signals. However, the secondembodiment is configured such that the signals outputted y from thefirst to fourth amplifiers 33-1 to 33-4 are supplied to a selectionswitch 51 which selects one of the signals supplied thereto to supplythe selected signal to the main A/D converter 34. Further, the gains ofthe first to fourth amplifiers 33-1 to 33-4 are the same as those in thefirst embodiment, and so the gain of the first amplifier 33-1 is set toone (1), the gain of the second amplifier 33-2 is set to two (2), thegain of the third amplifier 33-3 is set to four (4), and the gain of thefourth amplifier 33-4 is set to eight (8). In addition, like the firstto fourth A/D converters 34-1 to 34-4 shown in FIG. 3, the main A/Dconverter 34 converts an input signal to a digital signal with highresolution to be required within its convertible level range.

The selection switch 51 is controlled depending upon the magnitude oflevel of an input signal, that is, depending upon a range (level range)to which the level of an incoming input signal belongs. For this reason,after an input signal has passed through the anti-aliasing filter 32, itis branched to a range selection A/D converter 52. This range selectionA/D converter 52 has its resolution considerably lower than that of themain A/D converter 34, but it operates by application of a samplingpulse the frequency of which is higher than the sampling frequency forthe main A/D converter 34, and the operation speed of the rangeselection A/D converter 52 is selected such that before the main A/Dconverter 34 receives a signal at one sample point, selection of one ofthe outputs of the amplifiers by the selection switch 51 has beencompleted as well as before the main A/D converter 34 receives a signalat the succeeding sample point, the selection switch 51 can carry out anext selection of one of the outputs of the amplifiers.

For example, from a clock generator 53 is generated a clock CK_(A) thefrequency of which is twice as high as the frequency of a sampling clockCK_(S) to be supplied to the main A/D converter 34, and the clock CK_(A)is supplied to the range selection A/D converter 52 thereby to operatethe A/D converter 52 to sample. At the same time, the clock CK_(A) isalso supplied to a sampling clock generation part 54 which in turndivides the frequency of the clock CK_(A) by 2 and controls or adjuststhe phase thereof. The frequency-divided clock is supplied to the mainA/D converter 34 as a sampling clock CK_(S).

The operations of the main A/D converter 34 and the range selection A/Dconverter 52 discussed above will be specifically described withreference to FIG. 10. As shown in FIG. 10A, for instance, it is assumedthat a clock CK_(A) having its period of T_(P) is generated from theclock generator 53, an input signal is sampled and converted to adigital signal in the range selection A/D converter 52 every clockCK_(A), and a time required to convert the sampled signal to a digitalsignal is T₁. In this case, as shown in FIG. 10B, a sampling clockCK_(S) having its period of 2T_(P) is supplied from the sampling clockgeneration part 54 to the main A/D converter 34 at the time point thatthe sampling clock CK_(S) is delayed in phase from each clock CK_(A) bymore than the time T₁. On the other hand, in the main A/D converter 34,assuming that a time required to convert the sampled signal to a digitalsignal is T₂ every sampling, in order to make the operation thereof asfast as possible, generally, the sampling period 2T_(P) of the main A/Dconverter 34 is set to one which is a little larger than the time T2required for A/D conversion.

The digital output of the range selection A/D converter 52 is suppliedto a switch control part 55. As will be understood from FIGS. 10A and10B, a control signal corresponding to an digital output every secondclock CK_(A) is supplied to the selection switch 51 through the switchcontrol part 55 thereby to control the switching operation of theselection switch 51. That is, the digital output of the range selectionA/D converter 52 is inputted to the switch control part 55 in which towhich range the level of the input signal supplied to the input terminal31 belongs is determined, and a control signal is generated in theswitch control part 55 on the basis of such determination and applied tothe selection switch 51, the control signal instructing as to whichoutput among the outputs of the amplifiers 33-1 to 33-4 is to beselected. As a result, the selection switch 51 is controlled to selectone amplifier instructed by the control signal applied thereto.

Like the above-mentioned first embodiment, in case the first to fourthamplifiers 33-1 to 33-4 are used, it may suffice to determine to whichrange among the four ranges the level of the input signal belongs.Accordingly, the range selection A/D converter 52 may suffice to outputfour range selection digital signals corresponding to the four ranges,and hence may be one which is capable of converting the level of aninput signal to a digital signal of at least two bits. In case ofconverting the level of an input signal to a digital signal of two bits,four range selection signals of “00”, “01”, “10” and “11”can beoutputted from the range selection A/D converter 52 and supplied to theswitch control part 55. Consequently, as shown in FIG. 9 for instance,it may be configured that in case the output digital signal is “00”, acontrol signal for selecting the amplifier 33-4 having its gain of 8, incase the output digital signal is “01”, a control signal for selectingthe amplifier 33-3 having its gain of 4, in case the output digitalsignal is “10”, a control signal for selecting the amplifier 33-2, andin case the output digital signal is “11”, a control signal forselecting the amplifier 33-1 are generated from the switch control part55 and applied to the selection switch 51 thereby to control the switch51 to connect the amplifier corresponding to each control signal to themain A/D converter 34.

With the construction as discussed above, an input signal that the mainA/D converter 34 is to sample is properly amplified by the correspondingamplifier depending upon the level of the input signal and is inputtedto the main A/D converter 34 immediately before the main A/D converter34 samples. Accordingly, it is apparent that the same function andeffects as in the first embodiment already described can be obtained,and explanation thereof will be omitted.

Since it is required that the selection switch 51 operates at highspeed, it may be constructed by a switch circuit using, for example, PINdiodes. In such case, the switch control part 55 will generate controlsignals each of which controls corresponding one of the PIN diodes ofthe selection switch 51 to turn on and/or off.

The output digital signal from the main A/D converter 34 is correctedand processed in the correction processing part 37 as in theabove-stated first embodiment. As selection information in such case,the control signals from the switch control part 55 or the output signalfrom the range selection A/D converter 52 can be used. The rangeselection A/D converter 52 is one having a few bits, and so it isavailable by low cost even it operates at high speed. Accordingly, asshown in FIG. 10C, it may be arranged that the period of the clockCK_(A) generated from the clock generator 53 is set to 2T_(P) that isequal to the period of the sampling clock CK_(S) outputted from thesampling clock generation part 54, and that as shown in FIG. 10D, thesampling clock CK_(S) is outputted from the sampling clock generationpart 54 by delaying the sampling clock CK_(S) from the clock CK_(A) by atime which is a little greater than the time T₁.

Further, in the second embodiment described above, in case there is apossibility that a whisker-like or impulse-like noise is generated dueto the switching operation of the selection switch 51, since the periodof the switching control of the selection switch 51 is the same as thatof the sampling clock CK_(S), the phase of the period of the switchingcontrol of the selection switch 51 may be shifted to such an extent thatthe generated noise is not sampled by the sampling clock CK_(S).

The above-discussed first and second embodiments are in common with eachother in the point that each is constructed such that an input signal isconcurrently inputted to a plurality of amplifiers the gains of whichare different from one another, and that depending upon to which rangethe level of the input signal belongs, the output of the correspondingamplifier is converted to a digital signal which is, in turn, selectedand outputted. In these embodiments, the first amplifier 33-1 having itsgain of 1 may be not used. That is, as shown in FIGS. 3 and 8 by abroken line, the circuit connection may be changed such that the outputof the anti-aliasing filter 32 can be supplied directly to the first A/Dconverter 34-1 or the selection switch 51. However, in view of makingthe input-output impedance and phase characteristic uniform, and thelike, it is preferable that the amplifier 33-1 having its gain of 1 isused. In addition, as mentioned above, the number of amplifiers is notlimited to four. Taking into consideration the fact that the amplifier33-1 having its gain of 1 may be omitted, it suffices that at least oneamplifier the gain of which is greater than 1 is used. If the number ofamplifiers is increased, there is obtained an advantage that an A/Dconverter that outputs a signal of a little bits, operates at high speedand is inexpensive may be used as an A/D converter for converting theoutput of selected one amplifier to a digital signal. Alternatively, ifthe number of bits of a signal outputted from each A/D converter is notchanged (decreased), the resolution of each A/D converter is improved.

Furthermore, in the first and second embodiments, though the levelcontrol of an input signal has been effected by use of amplifiers, theymay be done by use of an attenuator or attenuators or by use of both anamplifier or amplifiers and an attenuator or attenuators. In short, itsuffices that at least one level controller is used. In addition, in thefirst and second embodiments, in case control for each level controllercan be precisely performed as requested, correction of thecharacteristic in the correction processing part 37 may be omitted.

Next, a third embodiment of the A/D conversion apparatus according tothe present invention will be described in detail with reference toFIGS. 11 to 13.

FIG. 11 is a block diagram showing a third embodiment of the A/Dconversion apparatus according to the present invention, and in FIG. 11,elements and portions corresponding to those in the first and secondembodiments will be denoted by the same reference numbers or charactersattached thereto and explanation thereof will be omitted unlessnecessary. In this third embodiment, an input signal from the inputterminal 31 is supplied, after it has passed through the anti-aliasingfilter 32, to first and second amplifiers (or two level controllers thatdiffer in their control variables from each other) 61-1 and 61-2. Thegains of the these amplifiers 61-1 and 61-2 are fixed, and in this thirdembodiment, the gain of the first amplifier 61-1 is set to one (1), andthe gain of the second amplifier 61-2 is set to eight (8). These gainsare merely by way of example, and they may be set to other values or maybe set to another values except for values of the power of 2 as in theabove example.

Outputs from the amplifiers 61-1 and 61-2 are supplied to correspondingfirst and second A/D converters 62-1 and 62-2, respectively. These A/Dconverters 62-1 and 62-2 have the same characteristic, that is, they areconfigured such that the convertible range in level of each of the A/Dconverters 62-1 and 62-2 is the same as well as they have the sameresolution, and they are operated by the same clock CK_(S) supplied froma clock terminal 35 thereby to convert outputs from the correspondingamplifiers 61-1 and 61-2 to digital signals with requested resolutionswithin their convertible level ranges. In addition, though not shown inthe figure, each of the A/D converters 62-1 and 62-2 is provided withthe sample-and-hold circuit 16 of the prior art A/D conversion apparatusshown in FIG. 1 built therein. Further, in case the sample-and-holdcircuit is not built therein, it is inserted before each of the A/Dconverters 62-1 and 62-2.

Output digital signals from the A/D converters 62-1 and 62-2 areinputted to a data selection part 63. The data selection part 63comprises a multiplexer 63-1 and a select signal generation part 63-2,and digital signals outputted from the A/D converters 62-1 and 62-2 areinputted to the multiplexer 63-1. The data selection part 63 selects aproper digital signal corresponding to the magnitude in level of theinput signal from the input terminal 31 and supplies the selecteddigital signal to a correction processing part 37. Like the above-statedfirst embodiment, the correction processing part 37 has a characteristiccorrection part and a scale correction part provided therein though notshown in the figure, and is constructed such that in case theinput-output characteristic of each of the amplifiers 61-1 and 61-2 isnot always different from a predetermined gain, a digital signalinputted to the correction processing part 37 may be corrected withreference to a first look-up table 45-1 or a second look-up table 45-2in characteristic correction part, and in the scale correction part, itmay be scaled down or up so that it has the same value as that of adigital signal obtained by directly digital-converting an input signaltransmitted to the input terminal 31.

In this third embodiment, the apparatus is arranged such that apre-estimated fluctuation range in the levels of input signals aredivided into two ranges, and depending upon to which divided level rangethe level of an input signal belongs, an output digital signal from thecorresponding A/D converter is selected. This switching of the range iscarried out by utilizing the fact that when the level of an input signalto the second A/D converter 62-2 is beyond the convertible level rangethereof, the second A/D converter 62-2 overflows so that theoverflow-bit of the converted output digital signal becomes “1”.Specifically, the digital signal outputted from the second A/D converter62-2 is also inputted to the select signal generation part 63-2 of thedata selection part 63, and when the overflow-bit of the digital signaloutputted from the second A/D converter 62-2 is “0”, the select signalgeneration part 63-2 supplies a select signal SEL2 (for example, asignal of logical high level) for selecting the second A/D converter62-2 to the multiplexer 63-1 thereby to cause the multiplexer 63-1 toselect the digital signal of the second A/D converter 62-2, and when thesecond A/D converter 62-2 overflows so that the overflow-bit of thedigital signal outputted therefrom becomes “1”, the select signalgeneration part 63-2 immediately supplies a select signal SEL1 (forexample, a signal of logical low level) for selecting the first A/Dconverter 62-1 to the multiplexer 63-1 thereby to cause the multiplexer63-1 to select the output digital signal of the first A/D converter62-1. In addition, when the digital signal of the first A/D converter62-1 is being selected, the overflow-bit of the output digital signal ofthe second A/D converter 62-2 turns to “0” and if this overflow-bit “0”does not turn to “1” within a preset time T10, the select signalgeneration part 63-2 supplies the select signal SEL2 to the multiplexer63-1 thereby to cause the multiplexer 63-1 to select the output digitalsignal of the second A/D converter 62-2. Further, only the overflow-bitof the digital signal outputted from the second A/D converter 62-2 maybe inputted to the select signal generation part 63-2.

For example, in case an input signal as shown in FIG. 12 by a solid line70 is supplied to the input terminal 31, assuming that a level forchanging the level range of this input signal 70, that is, an operationlevel for determining that an output from which one of the amplifiersshould be A/D converted, is denoted by L1 as shown in the figure, whilethe level of the input signal is lower than L1, a digital signal isselected, which is obtained by A/D converting the output of the secondamplifier 61-2 having its gain of 8, and when the level of the inputsignal comes to larger than L1, a digital signal is selected at once,which is obtained by A/D converting the output of the first amplifier61-1 having its gain of 1. In addition, while the digital signalobtained by A/D converting the output of the first amplifier 61-1 havingits gain of 1 is being selected because the level of the input signalhas come to larger than L1, the overflow-bit of the output digitalsignal of the second A/D converter 62-2 turns to “0” and if thisoverflow-bit “0” does not turn to “1” within a preset time T10, then thedigital signal obtained by A/D converting the output of the secondamplifier 61-2 having its gain of 8 is selected.

A relationship between the overflow-bit of the second A/D converter 62-2and the select signals outputted from the select signal generation part63-2 is shown in FIG. 13 by a time chart. In case the overflow-bit ofthe second A/D converter 62-2 is “0” as well as goes to “0” from “1” andcontinues to keep “0” during and after the preset time T10 has passed,the select signal generation part 63-2 outputs the select signal SEL2for selecting the output digital signal of the second A/D converter 62-2and supplies it to the multiplexer 63-1. On the other hand, it will beeasily understood that when the overflow-bit of the second A/D converter62-2 goes to “1” from “0”, the select signal generation part 63-2immediately outputs the select signal SEL1 for selecting the outputdigital signal of the first A/D converter 62-1 and supplies it to themultiplexer 63-1, and yet, the select signal generation part 63-2continues to output the select signal SEL1 even if the overflow-bit goesto “0” from “1” and if a time that the overflow-bit remains “0” isshorter than the preset time T10.

Further, the above-stated preset time T10 is set to the optimum timetaking signals to be measured and various requirements of measuringinstruments or apparatus into consideration, and for example, may be setto 1/RBW (resolution bandwidth).

As stated above, the third embodiment is arranged such that an inputsignal is concurrently inputted to two amplifiers the gains of which isdifferent from each other, and there is selected a digital signal whichis amplified by one of the amplifiers corresponding to the most suitablerange for the input signal (the level range of the input signal) andconverted by the corresponding A/D converter by utilization of theoverflow-bit of the digital signal outputted from the second A/Dconverter 62-2 every sample. Accordingly, for each sample, an inputsignal is amplified by an amplifier having its gain corresponding to thelevel of the sample data so that the level thereof comes within theproper convertible level range of the corresponding A/D converter, andthen it is converted to a digital signal by the corresponding A/Dconverter, this digital signal being selected. Therefore, as comparedwith the case that the gain of the amplifier is controlled for pluralsamples like the prior art shown in FIG. 2A, a digital signal withhigher accuracy can be obtained. In addition, the gain of each amplifieris not controlled at all, and a digital signal is selected, which isobtained by A/D converting the output amplified by corresponding oneamplifier. Accordingly, there is no possibility that any whisker-like orimpulse-like noise is generated due to control of the gain.

Further, in the third embodiment, too, the first amplifier 61-1 havingits gain of 1 may be not used. That is, as in the aforementioned firstand second embodiments, the circuit connection may be changed such thatthe output of the anti-aliasing filter 32 can be supplied directly tothe first A/D converter 62-1. However, in view of making theinput-output impedance and phase characteristic uniform, and the like,it is preferable that the amplifier 61-1 having its gain of 1 is used.In addition, taking into consideration the fact that the amplifier 61-1having its gain of 1 may be omitted, it suffices that at least oneamplifier the gain of which is greater than 1 is used. Moreover, thoughthe level control of an input signal has been effected by use ofamplifiers, they may be done by use of an attenuator or attenuators orby use of both an amplifier or amplifiers and an attenuator orattenuators. In short, it suffices that at least one level controller isused. In such case, if control for each level controller can beprecisely performed as requested, correction of the characteristic inthe correction processing part 37 may be omitted.

In the third embodiment, an amplifier the gain of which is fixed hasbeen used as the second amplifier 61-2, and it may be constructed suchthat an amplifier the gain of which is variable is used as the secondamplifier 61-2 and when the setting of the measuring resolutionbandwidth of a measuring apparatus is changed, the gain of this variablegain amplifier is changed and set to the optimum fixed value before themeasurement is started.

FIG. 14 is a block diagram showing a fourth embodiment of the A/Dconversion apparatus according to the present invention. As statedabove, this fourth embodiment is constructed such that a variable gainamplifier is used as the second amplifier and when the setting of themeasuring resolution bandwidth of a measuring apparatus is changed, thegain of this variable gain amplifier is set to the optimum fixed valuebefore the measurement is started.

As is clear from FIG. 14, in the fourth embodiment, there are providedfirst and second amplifiers 61-1 and 61-2 as well as first and secondA/D converters 62-1 and 62-2 for converting outputs of these amplifiers61-1 and 61-2 to digital signals respectively. Except that the gain ofthe first amplifier 61-1 is set to one (1), and the gain (N) of thesecond amplifier 61-2 is variable, other arrangement and/or constructionthereof is similar to that of the first embodiment, and so in FIG. 14,elements and portions corresponding to those in the first and thirdembodiments will be denoted by the same reference numbers or charactersattached thereto and explanation thereof will be omitted unlessnecessary.

As mentioned above, when the setting of the measuring resolutionbandwidth of a measuring apparatus is changed, the gain (N) of thesecond amplifier 61-2 is previously set to the optimum fixed value (forexample, a specified fixed value such as 2, 4 or 8 corresponding to thesetting of the measuring resolution bandwidth) before the measurement isstarted. A digital signal selected by the data selection part 36 iscorrected and processed in the correction processing part 37.Thereafter, further necessary processing for the digital signal isexecuted in a digital signal processing part subsequent to thecorrection processing part 37, and for example, it is requested that themore the bandwidth of a resolution bandwidth filter becomes narrow, themore the dynamic ranges of the A/D converters 62-1 and 62-2 are wide.Accordingly, if the gain of the second amplifier 61-2 is made variablelike the fourth embodiment and when the measuring resolution bandwidthis set before the measurement is started, the gain of the secondamplifier 61-2 is set, simultaneously therewith, to the optimum value(fixed value) corresponding to this set measuring resolution bandwidth,an input signal can be converted to a digital signal with high accuracy.

With the construction as discussed above, there is selected a digitalsignal which is amplified by one amplifier corresponding to the mostsuitable range for an input signal (the level range of an input signal)and converted by the corresponding A/D converter by utilization of thedigital signals outputted from the A/D converters 62-1 and 62-2 everysample. Accordingly, it is apparent that the same function and effectsas in the first embodiment already described can be obtained, andexplanation thereof will be omitted.

Further, in the fourth embodiment, too, the first amplifier 61-1 havingits gain of 1 may be not used. That is, as in the aforementioned firstand second embodiments, the circuit connection may be changed such thatthe output of the anti-aliasing filter 32 can be supplied directly tothe first A/D converter 62-1. However, in view of making theinput-output impedance and phase characteristic uniform, and the like,it is preferable that the amplifier 61-1 having its gain of 1 is used.In addition, though the level control of an input signal has beeneffected by use of the amplifiers, they may be done by use of anattenuator or attenuators or by use of both an amplifier or amplifiersand an attenuator or attenuators. In short, it suffices that at leastone level controller is used. In such case, if control for each levelcontroller can be precisely performed as requested, correction of thecharacteristic in the correction processing part 37 may be omitted.

As is clear from the foregoing, in accordance with the presentinvention, for each sample of an input signal, a level range suitablefor the input signal is determined, and the input signal is converted toa digital signal after it is controlled in its level in accordancetherewith or without controlling its level. Therefore, there is no needto use any envelope detector and any gain controller like the prior art,and so a remarkable advantage is obtained that any input signal can beconverted to a digital signal with high precision. In addition, an inputsignal is controlled in its level by each level controller and convertedto a digital signal, and this converted digital signal is selected. As aresult, a higher accurate digital signal is obtained, and yet, there isno possibility that any whisker-like or impulse-like noise is generateddue to control of the gain.

While the present invention has been described with regard to thepreferred embodiments shown by way of example, it will be apparent tothose skilled in the art that various modifications, alterations,changes, and/or minor improvements of the embodiments described abovecan be made without departing from the spirit and the scope of thepresent invention. Accordingly, it should be understood that the presentinvention is not limited to the illustrated embodiments, and is intendedto encompass all such modifications, alterations, changes, and/or minorimprovements falling within the scope of the invention defined by theappended claims.

1. An analog-to-digital conversion apparatus comprising: at least onelevel controller that controls the level of an input signal; a pluralityof analog-to-digital converters, wherein an analog-to-digital converterconverts the input signal, the level of which is not controlled, to adigital signal; and wherein at least one of the plurality ofanalog-to-digital converters is coupled to a corresponding levelcontroller to convert the input signal, the level of which is controlledby the corresponding level controller, to a digital signal; andselection means that selects and outputs one of the digital signalsconverted respectively by the plurality of analog-to-digital convertersdepending upon levels of the digital signals.
 2. The analog-to-digitalconversion apparatus as set forth in claim 1, wherein said selectionselects, in case the plural analog-to-digital converters are ranked inorder of the magnitudes of the levels of input signals inputted thereto,the output digital signal of the analog-to-digital convertor theoverflow-bit of which is “0” and the rank of which is immediately lowerthan that of the analog-to-digital converter the overflow-bit of theoutput digital signal of which is “1”.
 3. The analog-to-digitalconversion apparatus as set forth in claim 1, wherein said selectionmeans comprises: a plurality of comparators each comparing the digitalsignal of each analog-to-digital converter with a reference value; andmeans that selects, in case the plural analog-to-digital converters areranked in order of the magnitudes of the levels of input signalsinputted thereto, the output digital signal of the analog-to-digitalconverter corresponding to one of the comparators the output of which islower than the reference value as wall as the rank of which isimmediately lower than that of the analog-to-digital convertercorresponding to another one of the comparators the output of which ishigher than the reference value.
 4. An analog-to-digital conversionapparatus comprising: a first analog-to-digital converter that convertsan input signal, the level of which is not controlled, to a digitalsignal; a level controller that controls the level of the input signal;a second analog-to-digital converter that converts the input signal thelevel of which is controlled by the level controller to a digitalsignal; and selection means that selects and outputs the digital signaloutputted from the first analog-to-digital converter when anoverflow-bit for the digital signal outputted from the secondanalog-to-digital converter changes from “0” to “1” and that remains theselection of the digital signal outputted from the firstanalog-to-digital converter when the overflow-bit for the digital signaloutputted front the second analog-to-digital converter changes from “1”to “0” if the stare of “0” changes to “1” within a preset time.
 5. Ananalog-to-digital conversion apparatus comprising: at least one levelcontroller that controls the level of an input signal; a mainanalog-to-digital converter; and selection means that comprises: a rangeselection analog-to-digital converter the resolution of which is lowerthan that of the main analog-to-digital convener end to which the inputsignal is inputted; and a selection switch for supplying to the mainanalog-to-digital converter an output signal from one level controlleror the input signal the level of which is not controlled, depending uponthe level of a digital signal converted by the range selectionanalog-to-digital converter.
 6. The analog-to-digital conversionapparatus as set forth in any one of claims 1 to 4, further including:selection information generation part for generating selectioninformation representing the state of selection of the digital signal;look-up tables in which for each level controller, the output correctioncharacteristic thereof is stored; and a characteristic correction partfor correcting the characteristic of the selected digital signal withreference to the look-up table depending upon the selection information.7. The analog-to-digital conversion apparatus as set forth in claim 5,further including: selection information generation part for generatingselection information representing the state of selection of the levelcontroller; look-up tables in which for each level controller, theoutput correction characteristic thereof is stored; and a characteristiccorrection part for correcting the characteristic of the digital signaloutputted from the main analog-to-digital convener with reference to oneof the look-up tables depending upon the selection information.
 8. Theanalog-to-digital conversion apparatus as set forth in any one of claims1 to 4, further including: selection information generation part forgenerating selection information representing the state of selection ofthe digital signal; look-up tables in which scale correction datadepending upon the level of an input signal are stored; and a scalecorrection part far correcting the selected digital signal to a digitalsignal corresponding to the magnitude of the level of the input signalwith reference to one of the look-up tables depending upon the selectioninformation.
 9. The analog-to-digital conversion apparatus as set forthin claim 5 or 7, further including: selection information generationpart for generating selection information representing the state ofselection of the level controller, look-up tables in which scalecorrection data depending upon the level of an input signal are stored;and a scale correction part for correcting the digital signal outputtedfrom the main analog-to-digital converter to a digital signalcorresponding to the magnitude of the level of the input signal withreference to one of the look-up tables depending upon the selectioninformation.
 10. The analog-to-digital conversion apparatus as set forthin claim 1, 4 or 5, wherein the level controller has its gain fixed. 11.The analog-to-digital conversion apparatus as set forth in claim 1, 4 or5, wherein the level controller has its gain that is previouslysettable.
 12. An analog-to-digital conversion method comprising:converting an input signal, the level of which is not controlled, afirst digital signal; controlling the level of the input signal;converting the input signal, the level of which is controlled, to asecond digital signal; and selecting the first digital signal when anoverflow-bit for the second digital signal is “1” and selecting thesecond digital signal when the overflow-bit for the second digitalsignal is “0”, wherein said selecting step further comprises selecting,when the overflow-bit for the second digital signal changes from “0” to“1”, the first digital signal, and retaining the selection of the firstdigital signal when the overflow-bit for the second digital signalchanges from “1” to “0” if the state of “0” changes to “1” within apreset time.
 13. The analog-to-digital conversion apparatus as set forthin claim 6, further including: selection information generation part forgenerating selection information representing the state of selection ofthe digital signal; look-up tables in which scale correction datadepending upon the level of an input signal are stored; and a scalecorrection part for correcting the selected digital signal to a digitalsignal corresponding to the magnitude of the level of the input signalwith reference to one of the look-up tables depending upon the selectioninformation.